Compositions and methods for chemical-mechanical polishing (CMP) the surface of a substrate are well known in the art. Polishing compositions (also known as polishing slurries, CMP slurries, and CMP compositions) typically contain an abrasive material in an aqueous carrier. A surface of a substrate is abraded to polish the surface by contacting the surface with a polishing pad and moving a polishing pad relative to the surface while maintaining a CMP slurry between the pad and the surface. Typical abrasive materials include silicon dioxide, cerium oxide, aluminum oxide, zirconium oxide, and tin oxide. U.S. Pat. No. 5,527,423 to Neville, et al., for example, describes a method for chemically-mechanically polishing a metal layer by contacting the surface with a polishing slurry comprising high purity fine metal oxide particles in an aqueous medium. Alternatively, the abrasive material may be incorporated into the polishing pad. U.S. Pat. No. 5,489,233 to Cook et al. discloses the use of polishing pads having a surface texture or pattern, and U.S. Pat. No. 5,958,794 to Bruxvoort et al. discloses a fixed abrasive polishing pad.
Conventional polishing systems and polishing methods typically are not entirely satisfactory at planarizing metal-containing semiconductor wafers. In particular, polishing compositions and polishing pads can have less than desirable polishing rates, and their use in the chemical-mechanical polishing of semiconductor surfaces can result in poor surface quality.
The difficulty in creating an effective polishing system for semiconductor wafers stems from the complexity of the semiconductor wafer. Semiconductor wafers are typically composed of a substrate on which a plurality of transistors has been formed. Integrated circuits are chemically and physically connected into a substrate by patterning regions in the substrate and layers on the substrate. To produce an operable semiconductor wafer and to maximize the yield, performance, and reliability of the wafer, it is desirable to polish select surfaces of the wafer (e.g., a metal-containing surface) without adversely affecting underlying structures or topography. In fact, various problems in semiconductor fabrication can occur if the process steps are not performed on wafer surfaces that are adequately planarized. Because the performance of a semiconductor wafer is directly associated with the planarity of its surface, it is crucial to use a polishing composition and method that results in a high polishing efficiency, uniformity, and removal rate and leaves a high quality polish with minimal surface defects.
In conventional CMP techniques, a substrate carrier or polishing head is mounted on a carrier assembly and positioned in contact with a polishing pad in a CMP apparatus. The carrier assembly provides a controllable pressure to the substrate, urging the substrate against the polishing pad. The pad is moved relative to the substrate by an external driving force. The relative movement of the pad and substrate serves to abrade the surface of the substrate to remove a portion of the material from the substrate surface, thereby polishing the substrate. The polishing of the substrate by the relative movement of the pad and the substrate typically is further aided by the chemical activity of the polishing composition and/or the mechanical activity of an abrasive suspended in the polishing composition.
Tungsten is increasing being used as a conductive material to form the interconnections in integrated circuit devices. One way to fabricate planar tungsten circuit traces on a silicon dioxide substrate is referred to as the damascene process. In accordance with this process, the silicon dioxide dielectric surface is patterned by a conventional dry etch process to form holes and trenches for vertical and horizontal interconnects. The patterned surface is coated with an adhesion-promoting layer such as titanium or tantalum and/or a diffusion barrier layer such as titanium nitride or tantalum nitride. The adhesion-promoting layer and/or the diffusion barrier layer are then over-coated with a tungsten layer. Chemical-mechanical polishing is employed to reduce the thickness of the tungsten over-layer, as well as the thickness of any adhesion-promoting layer and/or diffusion barrier layer, until a planar surface that exposes elevated portions of the silicon dioxide surface is obtained. The vias and trenches remain filled with electrically conductive tungsten forming the circuit interconnects.
There is an ongoing need to develop new particulate abrasives for use in CMP compositions that are capable of polishing a semiconductor substrate, particularly a tungsten-containing substrate with a relatively low level of microdefects (i.e., low defectivity), while maintaining suitable polishing removal rates. The present invention provides such materials and CMP compositions. These and other advantages of the invention, as well as additional inventive features, will be apparent from the description of the invention provided herein.